3D Logic Integration

For many years, the semiconductor industry has continued to scale down the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) to increase the number of transistors per area unit, thus enhancing the performances of ICs. However, the transistor dimensions are reaching physical limits: as current transistors are now in the low nanometer range, some dimensions, such as the channel length, cannot be decreased further and CMOS scaling is predicted to reach an end in 2024. Therefore, alternative routes are investigated to keep sustaining the need for more powerful ICs.

In particular, in recent years, three-dimensional integrated circuits (3D IC) have been proposed. A 3D IC is an integrated circuit manufactured by stacking silicon wafers, dies or transistors and interconnecting them vertically to achieve performance improvements at reduced power and smaller footprint when compared to conventional 2D approaches. In other words, 3D IC is an integration scheme that exploits the z-direction to achieve electrical performance benefits while traditional ICs only exploit the x and y-directions with a single transistor layer. A typical example where 3D stacking can be useful is in stacking memory on top of logic circuits for a microprocessor.

For this research project, we aim at developing a domain-specific instruction-set processor in a 3D fashion. While conventional 3D ICs generally stack both transistors and interconnections several times, hence increasing the cost of fabrication, we propose here to use a very reduced scheme of interconnections to design a 3D circuit at a minimized cost.

This research effort is funded by an IMEC research agreement.