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A 32mW nanofiber-optimized interface based on a relaxation oscillator featuring 12 analog-front end and a digital controller
A 32mW nanofiber-optimized interface based on a relaxation oscillator featuring 12 analog-front end and a digital controller
This ASIC can interface up to 12 gas sensors with <1mA power consumption per channel. The digital controller computes the gas sensors response and transmit it over UART every 100ms. Resistance can vary from 100 kOhm to 50 GOhm.Â
Designer: Matthieu Couriol
Technology: TSMC 180nm
A Universal Low-power, Low-cost, Resistive Sensor Interface for Gas Sensor Arrays
A Universal Low-power, Low-cost, Resistive Sensor Interface for Gas Sensor Arrays
The goal of this ASIC is to provide a low-power, low-cost solution to interface a very wide range of chemi-resistive gas sensors with industrial standard communication protocols. Resistances can very from 5kOhms up to 50Gohms
Designer: Matthieu Couriol
Technology: TSMC 180nm
A 10-pA Resolution Mixed-Signal Fully Discrete Sigma Delta ADC Topology for Chemiresistive Sensor-Based Application
A 10-pA Resolution Mixed-Signal Fully Discrete Sigma Delta ADC Topology for Chemiresistive Sensor-Based Application
The goal of this test vehicle is to interface chemi-resistive sensors based on a novel sigma-delta ADC topology.
Designer: Matthieu Couriol
Technology: TSMC 180nm
First OpenFPGA Proof of Concept
First OpenFPGA Proof of Concept
The goal of this test vehicle is to provide the very first proof of concept of OpenFPGA, an FPGA IP generator. It consists of a 2x2 SRAM-based FPGA.
Designer: Edouard Giacomin
Technology: GF 130nm
A 130nm RRAM-based FPGA
A 130nm RRAM-based FPGA
The goal of this test vehicle is to evaluate the functionality and performances of some RRAM-based FPGA.
Designer: Edouard Giacomin
Technology: ST 130nm
Courtesy of LETI - Etienne Nowak
A 130nm RRAM-based Configurable Logic Block Test Vehicle
A 130nm RRAM-based Configurable Logic Block Test Vehicle
The goal of this test vehicle is to evaluate the functionality of a RRAM-based CLB.
Designer: Edouard Giacomin
Technology: ST 130nm
Courtesy of LETI - Etienne Nowak
A 130nm RRAM Circuit Exploration Test Vehicle
A 130nm RRAM Circuit Exploration Test Vehicle
The goal of this test vehicle is to evaluate the functionality and performances of several RRAM blocks: Non-Volatile D Flip-Flop (NVDFF), RRAM-based multiplexers, 1T1R and 4T1R programming structures.
Designer: Edouard Giacomin
Technology: ST 130nm
Courtesy of LETI - Etienne Nowak
A 180nm RRAM Technological Characterization Test Vehicle
A 180nm RRAM Technological Characterization Test Vehicle
This test vehicle is intended to perform a technology characterization about our RRAM technology at the University of Utah. It is composed of 3 crossbar arrays of 1T1R (1 Transistor 1 RRAM) programming structures and 1 crossbar array of 1T1TR (1 Transistor, 1 Transistor as a RRAM). In total, there are 1512 1T1R cells and 504 1T1TR cells.
Designer: Edouard Giacomin
Technology: UMC 180nm
A 180nm RRAM Circuit Exploration Test Vehicle
A 180nm RRAM Circuit Exploration Test Vehicle
The goal of this test vehicle is to evaluate the functionality and performances of some RRAMs blocks. Non-Volatile D Flip-Flop (NVDFF), RRAM-based multiplexers and 4T1R (4 Transistors 1 RRAM) programming structures have been implemented.
Designer: Edouard Giacomin
Technology: UMC 180nm
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