Lab Presentation and Open Positions
The Laboratory for NanoIntegrated Systems (LNIS) research aims at developing low-power high-performance versatile computing systems by exploring the opportunities coming from novel EDA techniques and their links to emerging device technologies. Projects are carried out in an interdisciplinary team with a wide range of competences and in close collaboration with other labs and partners.
Prospective PhD and MSc/BSc students are encouraged to apply to the research group at the University of Utah.
Interested applicants shoud send a CV and a research statement by e-mail to Dr. Gaillardon at the following address:
6/14/22: Check out Ganesh PhD Story!
5/17/22: "Approximate Logic Synthesis by Combining Two and Multi-Level Digital Circuits" won the 2022 Best Paper - Graduate Work at the South Symposium on Microelectronics. Congratulations Walter and team!
3/24/2022: Welcome Alexandre!
3/1/2022: We welcome to Olivia and Raven to the team! and the paper "Improving LUT-Based Optimization for ASIC" was accepted to DAC 2022, congratulations Walter!
1/19/2022: "An Open-Source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis" was accepted to ISCAS 2022, congratulations Roman and Ashton!
1/11/2022: Check out LNIS first PhD Story!
12/29/2021: Walter's PhD Logic Synthesis in the Machine Learning Era: Improving Correlation and Heuristics has been accepted to the DATE 2022 PhD Forum, congratulations!
12/26/2021: The paper A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal in collaboration with UFRGS was accepted to Transactions on Computer-Aided Design of Integrated Circuits and Systems, congratulations Walter!
11/29/2021: The paper A Multiply-And-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow was accepted to TNANO, congratulations Edouard.
10/17/2021: Our project on Microfluidics was funded, and we welcome Daniel to the team !
09/20/2021: The paper LSOracle 2.0: Capabilities, Integration, and Performance was accepted to WOSET 2021, congratulations Scott.
08/15/2021: Welcome to Allen!
07/14/2021: The paper Exploring eFPGA-based Redaction for IP Protection was accepted to ICCAD 2021, congratulation to the team effort!
07/04/2021: Two papers: A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors and A 12 pA Sigma Delta ADC Topology for Chemiresistive Sensor-Based Application were accepted to VLSI SOC 2021, congratulations Matthieu!
06/23/2021: The following papers were accepted to IWLS 2021: A Supervised Learning Approach for Technology Mapping, congratulations Walter; and Structure Aware Partitioning for Mixed LogicSynthesis, congratulations Ashton and Scott!
06/09/2021: Check out our FROG Testchip Bringup video.
05/17/2021: LNIS welcomes 3 team members: Andrew, Dan and Dillon. Welcome!
04/07/2021: Edouard successfully defended his PhD. Congrats!
03/29/2021: The paper Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors was accepted to JEDS. Congratulations Patsy!
03/25/2021: The LNIS welcomes two team members: Lea as a short-term scholar and Roman, a Post-doctoral Researcher.
03/15/2021: The paper "SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping" was accepted to the 58th Design Automation Conference (DAC). Congrats to Walter!
03/10/2021: The LNIS welcomes three undergraduate students to our research activities : Faris, Ben and Nichols.
01/29/2020: Two papers have been accepted at the ISCAS 2021 conference. Congrats to Aurelien and Edouard!
01/25/2020: The LNIS welcomes 3 members: Clara, Will, and Andrew!
12/21/2020: Corinne joined the lab as a Research Staff. Welcome aboard!
12/11/2020: The poster "A Two-level Approximated Synthesis Method," won the 2nd best poster award at the 1st IEEE CASS/CEDA Seasonal School on Electronic Design Automation.
12/07/2020: Paper "Extending Boolean Methods for Scalable Logic Synthesis" has been accepted by IEEE Access.
11/25/2020: The poster "Smart-Redundancy: a new SEU & SET Mitigation Method for FPGAs" has been accepted by the SERESSA workshop. Congrats to Aurelien!
11/23/2020: The LNIS welcomes a new senior software developer: welcome to Ashton!
11/17/2020: Patsy presents her research on TIGFETs as part of the University of Utah IEEE chapter. Information and Zoom link here.
11/15/2020: Paper "A Deep Learning Approach of Sensor Fusion Inference at the Edge" has been accepted by the DATE 2021 conference. Congrats to Tom!
11/14/2020: Paper "A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs" has been accepted by the ISPD 2021 conference. Congrats to Ganesh!
11/5/2020: Paper "OpenFPGA: Towards Automated Prototyping for Versatile FPGAs" was selected as the Best contribution award at the WOSET 2020 workshop. Congrats to everyone!
10/15/2020: 2 papers have been accepted by the WOSET2020 workshop.
09/12/2020: Paper "Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization" has been accepted by the ASP-DAC 2021 conference. Congrats to Walter!
09/10/2020: The LNIS welcomes three new members: Grant, Clément and Nate. Welcome!
09/01/2020: An article about curb air pollution monitoring has been released by the COE from the University of Utah.