Controllable-Polarity Transistors and Digital Circuits
Vertically-stacked NanoWire FETs (SiNWFETs) with Gate-All-Around (GAA) structures are the natural and most advanced extension of FinFETs. Indeed, by splitting the 2-D thin film channel into a collection of 1-D elements, such a device exhibits superior electrostatic control. In the nanometer regime, Schottky contacts at channel interfaces are becoming challenging to avoid. Hence, devices can face an ambipolar behavior where they exhibit n- and p-type characteristics simultaneously. While most modern technology targets the suppression of this behavior with the addition of complex process steps, a new device concept involves exploiting this phenomenon to increase switching functionality. By engineering the source and drain contacts to be perfectly mid-gap and constructing independent double-gate structures, the device polarity can be electrostatically forced to either n- or p-type-type depending on the second gate bias, enabling device reconfigurability. The in-field polarizability of a device enables the development of new logic architectures which are intrinsically not implementable in CMOS in a compact form.
Recently, the group succeeded in fabricating controllable-polarity transistors based on arrays of Double-Gate vertically-stacked Silicon NanoWire FETs (DG-SiNWFETs). Schottky contacts and double-gate structure ensure the controllable polarity. Fig. 1 depicts a conceptual sketch of the proposed device, an SEM picture of the fabricated device and an I-V curve to better grasp its behavior. The short-term integration of novel devices in very large-scale systems relies on CMOS investments so the process flow has been developed to be fully compatible with top-down CMOS technology.
Fig. 1: (a) Conceptual drawing of the SiNWFET and the associated device symbol. Source/Drain pillars (green) support a vertical stack of nanowires. The nanowires are surrounded by GAA Polarity Gate (violet) and Control Gate (red). (b) Tilted SEM view of an array of fabricated devices. (c) I-V characteristics of the optimized device.
Controllable-polarity devices are logical bi-conditional on both gate values. As compared to MOS transistors that naturally implement the NOT function, controllable-polarity devices have an extended functionality, as they enable a compact realization of XOR- and MAJ-based logic functions. Fig. 2 highlights this compactness by showing the schematic of 2-input XOR and 3-input MAJ gates, realized with only four controllable-polarity devices. As a direct consequence, the data paths of digital circuits - typically rich in XOR and MAJ functions - can be implemented with the same efficiency of control logic. Therefore, in addition to device developments, the investigation of physical design techniques of hyper regular structures and new synthesis methodologies open a broad research horizon towards supporting the higher expressive power brought by controllable-polarity devices.
Fig. 2: (a) Full-swing static 2-input XOR and (b) Transmission-style 3-input MAJ logic gates.
This research is focused on the design, process development, fabrication, and testing of complex Three-Independent-Gate FET (TIGFET) systems - a natural extension of the previously fabricated DG-SiNWFETs - which will allow not only for the dynamic reconfiguration of device polarity, but also enhanced control of the threshold voltage not achievable with conventional MOSFET devices, and the ability to attain super steep subthreshold slope (S4) characteristics.
This research effort is funded by the NSF Career Award number 1751064 and the SRC Contract 2018-IN-2834.